1. Field of the Invention
The present invention relates to error prevention devices and, more specifically, to a device that prevents errors due to cosmic rays.
2. Description of the Prior Art
Microelectronic devices operated in space and high altitudes are typically subjected to a barrage of charged particles that often strip electrons or the create electron/hole pairs. Such interference can result in signal spikes, noise, and single-effect events (SEE). SEEs can have a significant impact on digital devices.
When a high-energy particle travels through a semiconductor, it leaves an ionized track behind. This ionization may cause a highly localized effect such as a benign glitch in output, a less benign bit flip in memory or a register, or (especially in high-power transistors) a destructive latch-up and burnout. Single event effects can be disruptive in satellites, aircraft, and other aerospace applications (both civilian and military).
There are several different types of SEE, including: (1) Single-event upsets (SEU), or transient radiation effects in electronics, are state changes of memory or register bits caused by a single ion interacting with a circuit. Generally, they do not cause lasting damage. However, in very sensitive devices a single ion can cause a multiple-bit upset (MBU) in several adjacent memory cells. SEUs can result in single-event functional interrupts (SEFI) when they cause a device to enter into an undefined state, a test mode, or a halt, each of which require a reset or a power cycle for a recovery. (2) Single-event latch-up (SEL) can occur in any chip with a parasitic PNPN structure. A heavy ion or a high-energy proton passing through one of the two inner-transistor junctions can open the thyristor-like structure, which then stays opened (an effect known as latch-up) until the device is power-cycled. As the effect occurs between the power source and the substrate, destructively high current can be involved and the part may fail. Bulk CMOS devices are most susceptible to this type of SEE. (3) Single-event transient (SET) occurs when the charge collected from an ionization event discharges in the form of a spurious signal traveling through the circuit. This corresponds to the effect of an electrostatic discharge. (4) Single-event snapback, similar to SEL but not requiring the PNPN structure, can be induced in N-channel MOS transistors switching large currents. When an ion hits near the drain junction, it can cause avalanche multiplication of the charge carriers. The transistor then opens and stays opened. (5) Single-event induced burnout (SEB) may occur in power MOSFETs when the substrate right under the source region gets forward-biased and the drain-source voltage is higher than the breakdown voltage of the parasitic structures. The resulting high current and local overheating then may destroy the device. (6) Single-event gate rupture (SEGR) may be observed in power MOSFETs when a heavy ion hits the gate region while a high voltage is applied to the gate. A local breakdown then occurs in the insulating layer of silicon dioxide, causing local overheat and destruction (looking like a microscopic explosion) of the gate region. It can occur in EEPROM cells during write or erase, when the cells are subjected to a comparatively high voltage.
The electronics industry has focused on protecting space born circuitry, such as memory (e.g. SRAM/DRAM), from the affects of SEE through use of radiation hardened (sometimes referred to as “RAD hard” circuitry). RAD hard circuitry uses both physical protection schemes and logical protection schemes. Typical physical protection schemes employ shielding, insulation and use of high band gap substrates to prevent SEEs. Typical logical protection schemes include redundancy and error detection and recovery schemes to mitigate the effects of SEEs.
A soft error is any error occurrence in a computer's memory system that changes an instruction in a program or a data value. A soft error will not damage a system's hardware; the only damage is to the data that is being processed. If detected, a soft error may be corrected by rewriting correct data in place of erroneous data. Highly reliable systems use error correction to correct soft errors as they occur. However, in many systems, it may be impossible to determine the correct data, or even to discover that an error is present at all. In addition, before the correction can occur, the system may have crashed, in which case the recovery procedure must include a reboot. Rebooting a microprocessor, especially for very sensitive and mission critical applications that are typically running in satellites, is usually not desirable and sometimes not even feasible.
Existing systems involve significant overhead and are not always reliable. They also lack the ability to take temporary and local steps to prevent the consequences of an interfering event—steps that allow return to normal operation upon completion of the interfering event.
Therefore, there is a need for a circuit protection system that detects cosmic rays that are about to interact with a circuit and that takes protective action before such interaction.